EDN

Virtually every ASIC ends up an FPGA

Over the past decade, designers around the world have argued over the relative merits of using ASICs or FPGAs to implement digital electronic designs. This ongoing discussion has typically positioned ...
EDN

FPGA-to-ASIC conversion a crucial concern

It is clear that FPGAs are great for prototyping and low-volume production. It's also clear, however, that any relatively complex mid- to high-volume design for which power consumption, component cost ...
AV Network

Justin Kennington on AV Supply Chain Using FPGA vs. ASIC Chips

SDVoE Alliance President, Justin Kennington shares his perspective on how FPGA versus ASIC chips impacts the product supply chain in the AV industry. When you purchase through links on our site, we ...
Business Wire

Faraday Unveiled FPGA-Go-ASIC Prototyping Platform to Accelerate FPGA-to-ASIC Conversion

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today unveiled its FPGA-Go-ASIC™ prototyping platform solution. This ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
Semiconductor Engineering

FPGA Design Tradeoffs Getting Tougher

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the ...
Digi Times

FPGA vs ASIC: Altera CEO highlights FPGA's advantage in AI era

Embedded World 2025 officially commenced this week in Nuremberg, Germany, with Sandra Rivera, CEO of FPGA company Altera, delivering the keynote address. In her presentation, Rivera discussed key ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Electronic Design

FPGAs Ride Tools Into ASIC Territory

When pondering your next-generation system design, you may ask yourself whether the spiraling mask costs have priced you out of the ASIC game. You'll perform the requisite analyses of performance ...
Electronic Design

5G Cellular Infrastructure and the Migration from FPGAs to Custom ASICs

As Zhengmao Li, executive vice president of the world’s biggest operator put it at MWC this year, 5G will require three times as many base stations to deliver the same coverage as LTE, will require ...
Forbes

The Evolution Of Programmable Hardware At Xilinx

This voice experience is generated by AI. Learn more. This voice experience is generated by AI. Learn more. I recently participated in an event that unveiled a new IEEE milestone for the field ...