ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.

Manual and automated IC-layout tools are integrated in the PEYE Yield Finder analysis software. The combined yield-driven, standard-cell, design optimization flow facilitates the application of design ...

The right tool for the job makes all the difference. Ever try hammering a nail in with a rock? How many nails did you ruin before you gave up? Or try to tighten a crucial bolt by hand? It takes ...

As integrated circuit (IC) designs have grown in complexity, scale and speed requirements, design rule checking (DRC) has evolved from a routine step into a critical pillar of successful tapeouts.