Semiconductor Engineering

Algorithm HW Framework That Minimizes Accuracy Degradation, Data Movement, And Energy Consumption Of DNN Accelerators (Georgia Tech)

This new research paper titled “An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators” was published by researchers at Georgia Tech. According to the ...
The Next Platform

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Learning?

Continued exponential growth of digital data of images, videos, and speech from sources such as social media and the internet-of-things is driving the need for analytics to make that data ...
Business Wire

Toshiba Image Recognition SoC for Automotive Applications Integrates a Deep Neural Network Accelerator

TOKYO--(BUSINESS WIRE)--Toshiba Electronic Devices & Storage Corporation (“Toshiba”) today announced development of an image recognition SoC (System on Chip) for automotive applications that ...
Electronic Design

DSP Takes on Deep Neural Networks

Machine learning (ML) and deep neural networks (DNNs) are topics that embedded designers are investigating and deploying, according to the recent Electronic Design’s Embedded Revolution survey.