Electronic Design

Verification Techniques For FPGA Designs

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...
Semiconductor Engineering

A New Strategy For Successful Block/Chip Design-Stage Verification

Achieving efficiency in integrated circuit (IC) design while maintaining design quality is not just a goal, but a necessity. Designers constantly strive to strike a balance between ever-tightening ...
EurekAlert!

New framework PyABV significantly enhances assertion verification capabilities of PyRTL

PyABV injects high-performance assertion engines into PyRTL, doubling verification coverage on complex HADM designs while ...
EDN

Verification Platform for Complex Designs

As the complexity of electronic designs continues to increase, the challenge of verifying their functional correctness is increasing as well. The problem is compounded with the increasing market ...
Semiconductor Engineering

A New Vision For Memory Chip Design And Verification

Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for ...
EDN

Commentary: SystemVerilog enables design with verification

The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts ...
Electronic Design

Verification And Software Dominate EDA’s Future

With the cost of design skyrocketing, EDA must hasten its transition from a hardware-centric industry to a software-centric one. Meanwhile, look for virtual platforms and transaction-level modeling to ...
Business Wire

Thinci Deploys Full Cadence Verification Suite for AI Designs, Accelerating Project Schedule by Months

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Thinci has deployed the full Cadence ® Verification Suite to accelerate the design and verification ...
Business Wire

NUVIA Selects Avery Design for Next Generation PCIe ® Verification

TEWKSBURY, Mass.--(BUSINESS WIRE)--Avery Design Systems, leader in functional verification solutions today announced NUVIA who is reimagining silicon in a new way, creating compute platforms that ...
Ars Technica

Breaking into ASIC Design/Verification

I'm fast approaching the one year mark with my current employer since I graduated last year. Previously, I did three four month work terms with them and they were for the most part interesting. I took ...
Ars Technica

ASIC design/verification or embedded systems programming

1. In a big company, doing ASIC design verification for a WCDMA modem for 3G cellular chips. 2. Small company, doing Embedded Software Programming. Working on the design and implementation of layer 1 ...