EDN

Tracking PLL design through the decades, part 2

The desire to integrate more gateshas driven two advances in CMOS-processingtechnology, enabling the integrationof practical inductors in genericCMOS-logic processes. The first, theuse of CMP ...
Design-Reuse

True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference

True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries. At the 62 nd Design Automation Conference ...
EDN

Two gates and a microprocessor form digital PLL

You can use Microchip's low-cost PIC16F818 microprocessor and a pair of gates to construct a digital PLL that can clean noisy digital signals over a range of 4 to 40 kHz. Featuring programmable lock ...
Electronic Design

All digital phase-locked loop offers sub-mW power consumption

San Francisco, CA. At the 2017 International Solid-State Circuits Conference in San Francisco, imec, Holst Centre, and ROHM presented an all-digital phase-locked loop (ADPLL) for Internet-of-Things ...
Design-Reuse

True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL that Offers Exceptional Performance, Features and Ease of Use

Los Altos, California, June 23, 2025 -- True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries ...
EurekAlert!

Powering the future: Smallest all-digital circuit opens doors to 5 nm next-gen semiconductor

Scientists at Tokyo Institute of Technology (Tokyo Tech) and Socionext Inc. have designed the world's smallest all-digital phase-locked loop (PLL). PLLs are critical clocking circuits in virtually all ...
Electronic Design

Digital PLL Perks Up Performance In T1-E1, Other TDM Apps

Thanks to a digital phase-locked loop (DPLL), the ZL30109 DS1/E1 System Synchronizer chip brings timing and synchronization to multitrunk DS1 and E1 transmission equipment. DPLLs typically use a DSP ...
EurekAlert!

Combating fractional spurs in phase locked loops to improve wireless system performance in Beyond 5G

Two innovative design techniques lead to substantial improvements in performance in fractional-N phase locked loops (PLLs), report scientists from Tokyo Tech. The proposed methods are aimed to ...
Nanowerk

Smallest all-digital circuit opens doors to 5 nm next-gen semiconductor

(Nanowerk News) Scientists at Tokyo Institute of Technology (Tokyo Tech) and Socionext Inc. have designed the world's smallest all-digital phase-locked loop (PLL) ("A Fully-Synthesizable Fractional-N ...