EDN

Front-end analysis accelerates ASIC flow

The problem for Infrant Technologies, a young network storage IC company, was to figure out how to avoid the typical iterative design scenario. For our latest design, a 250-MHz network storage device ...
EDN

FPGA Front End Streamlines Transition to ASIC

Altera Corporation announced the HardCopy II family, its next-generation structured ASIC solution. HardCopy II devices are the industry's most compelling structured ASICs, featuring a unique FPGA ...
Electronic Design

ASIC Handoff Gets Physical As Front And Back Ends Converge

True or false: ASIC design follows a very straightforward path that begins with high-level architectural definition. It proceeds through RTL design and preliminary floorplanning. After synthesis, the ...
Digi Times

ASIC Shift for High-Speed Computing: PGC's Design Service Turnkey Platform Speeds Time-to-Market

As AI workloads move from cloud to edge, the volume of image and sensor data across industries is rising rapidly. Edge devices that previously relied on FPGAs and off-the-shelf modules are now running ...