EDN

Verific’s Netlist-Only Parser Used in Achronix CAD Environment

Verific Design Automation today announced that Achronix Semiconductor Corporation, developer of the world’s fastest field programmable gate array (FPGA) called Speedster, uses Verific’s Netlist-Only ...
EDN

Verific Design Automation’s Netlist Only Parser, Database

Verific Design Automation, best known for its Verilog, SystemVerilog and VHDL parsers and elaborators, today said that its Netlist Only Parser is gaining momentum among electronic design automation ...
Semiconductor Engineering

Leveraging Symbolic Simulations For IO Verification

IO libraries and interface IPs are an important part of any integrated circuit design that needs to communicate with the outside world or other integrated circuits. Interface IPs are the literal ...
Electronic Design

Mixed-Signal Simulator Speaks Verilog-AMS

Designers today find themselves adding more and more analog and mixed-signal content to their creations. And at nanometer geometries and gigabit speeds, digital circuits begin to look more analog than ...
Design-Reuse

Pitfalls for Logical Equivalence Check

The VLSI design cycle is partitioned into two phases i.e. front-end and back-end phases of the complete SoC design cycle. While at front-end, most of the architectural specifications, coding and ...
Design-Reuse

Designing Around an Encrypted Netlist: Is The Pain Worth the Gain?

Oftentimes, in order to save on the cost of IP, a company will select an encrypted netlist as the deliverable instead of the RTL source code. This is especially common among companies looking to ...