Semiconductor Engineering

Power Gating And Power-Centric Programing

SoC design has a number of techniques for power management. One of the more prevalent methods is to use power gating to turn on and off blocks based on applications being run, and mode controls. Power ...
EDN

Demystify power gating and stop leakage cold

Low power or power efficiency is a key design requirement for nanometer designs today. The market for consumer and wireless devices is rapidly changing, driven by the convergence of applications, ...
EDN

NEMS eyed for CMOS power gating

The steady rise in leakage power over the last decade has made low-power design an exceedingly difficult problem mainly because attempts to control leakage power tend to negatively impact performance ...
Semiconductor Engineering

Nano Gap MEMS Switches for Power Gating in Low Power Systems (KAIST, Chonnam National Univ.)

A new technical paper titled “Ultra-Fast, Low-Resistance Nano Gap Electromechanical Switch for Power Gating Applications” was published by researchers at KAIST and Chonnam National University. “The ...
TechRepublic

Power Optimization of 8:1 MUX Using Transmission Gate Logic (TGL) with Power Gating Technique

In this paper, the authors aim at reducing power and energy dissipation in Transmission Gate Logic (TGL) multiplexer CMOS circuits comprise of reducing the power supply voltages, power supply current ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...