EDN

VHDL 101 – IF, CASE, and WHEN in a Process

Last time, in the third installment of VHDL we discussed logic gates and Adders. Let’s move on to some basic VHDL structure. All HDL languages bridge what for many feels like a strange brew of ...
Design-Reuse

Open-source Framework and Practical Considerations for Translating RTL VHDL to SystemC

SystemC has gained wide acceptance in the design of new digital IPs. However, there are numerous IPs already designed in VHDL. With the advances in SystemC ecosystem, like IEEE standardization, TLM-2 ...
EDN

Accellera Supports VHDL 4.0 Standard and IEEE 1076™-2008 Ratification

San Jose, Calif., DVCon, February 20, 2008, — Accellera, the electronics industry organization focused on Electronic Design Automation (EDA) standards, announced today that its members and Board of ...