SAN FRANCISCO — The International Solid State Circuits Conference (ISSCC) renewed a running debate over the suitability of CMOS for radio frequency circuits in a heavily attended evening panel session ...
Levering their digital CMOS 65 nm process, Fujitsu announced this morning availability of PDKs and shuttle runs for a 65 nm RF CMOS process. Offering MIM and MOS capacitors, thick metal inductors, and ...
Toshiba Electronics Europe’s ASIC Foundry Business Unit has announced a new generation of technologies and services for speeding the development and reducing the cost of system-on-a-chip (SoC) RF ICs ...
NEWPORT BEACH, Calif.--(BUSINESS WIRE)--TowerJazz, the global specialty foundry leader, today announced the availability of enhanced RF SOI CMOS and high speed SiGe process design kits (PDKs) for its ...
The next-generation 4G wireless standard known as long-term evolution (LTE) presents some new and difficult design choices for OEMs. One of the more difficult choices involves the less glamorous, but ...
Munich, Germany, July 19, 2006-- Infineon Technologies AG (FSE/NYSE: IFX), a leading provider of communication chips, today announced successful tape-out of a dual-band UWB (Ultra-Wideband) Radio ...
LANDSHUT, Germany & MUNICH--(BUSINESS WIRE)--LFoundry today announced the availability of an OpenAccess (OA) based interoperable process design kit (iPDK) for high performance analog and RF design ...
Today’s consumer, communication, and computer electronic devices have clocks, communication interfaces, and high-speed signal-conditioning circuits that operate at radio frequencies (RF). Providing ...
Taiwan Semiconductor Manufacturing Company (TSMC) began volume production of mobile phone RF transceivers using 0.18-micron RF CMOS (complementary metal-oxide semiconductor) processing for US-based ...
Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the ...
It’s very difficult to create accurate device-simulation models for advanced CMOS digital processes. Why? Because hard-to-model effects like gate accumulation and tunneling, trap-assisted tunneling, ...
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