Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that ...

Every day, more applications are deploying artificial intelligence (AI) system to increase automation beyond traditional systems. The continuous growth in computing demands of AI systems require ...

Over the last few years, design-for-test (DFT) chip-testing techniques such as internal scan (ISCAN), automatic test-pattern generation (ATPG), built-in self-test (BIST), and boundary scan (BSCAN) ...

The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques.

Shipping high-quality ICs requires that design-for-test (DFT) methodologies be included in a design. DFT provides external access at the device’s I/O pins to internal registers to either control or ...

After 20 years offering training and consulting services for the chip- and board-test design community, Dr. Ben Bennetts, founder of Bennetts Associates, has transferred his board-level ...

What is CTL, and why is it important to the semiconductor industry? The answers are here. Although the IEEE 1450.0 Stand-ard Test Interface Language (STIL) was adopted in March 1999, widespread ...