Automation has become the backbone of modern SystemVerilog/UVM verification environments. As designs scale from block-level modules to full system-on-chips (SoCs), engineers rely heavily on scripts to ...

Driven by the explosion of big data and expanding applications, chip design complexity is increasing. Applications such as high-performance computing (HPC), the Internet of Things (IoT), automotive, ...

The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end ...

Most companies use a bottom-up verification flow, which has some implications on the tools that they use for verification. Some companies, though, are moving to a top-down flow because today’s systems ...

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...

Researchers from the National University of Defense Technology (NUDT) in Changsha have introduced a first-of-its-kind framework, PyABV, that seamlessly integrates assertion-based verification into the ...