Phys.org

Samsung’s ViP Design Methodology Reduces SoC Design Time Up to 40 Percent

Samsung Electronics Co., Ltd., a leader in advanced semiconductor technology, today revealed a hardware/software co-design methodology that will reduce overall design time for the company’s ...
Business Wire

Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs

TEWKSBURY, Mass.--(BUSINESS WIRE)--Avery Design Systems, leader in functional verification solutions today announced the pre-silicon system simulation solution of NVMe TM SSD and PCIe® designs using ...
Design-Reuse

Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet applications to Achieve Compliance and High-Speed Connectivity

Tewksbury, MA., June 21, 2022 — Avery Design Systems, a leader in functional verification solutions, today announced it has been chosen by eTopus as its verification IP solution partner for eTopus ...
Design-Reuse

Avery Design Announces CXL 2.0 VIP

Tewksbury, MA., January 25, 2021 — Avery Design Systems, leader in functional verification solutions today announced availability of CXL 2.0 VIP. Computer Express Link TM (CXL) is an open ...